1. Field of the Invention
The present invention relates to interrupt detection apparatuses, and particularly relates to an interrupt detection apparatus which detects an interrupt message including address information and an information processing system including the interrupt detection apparatus.
2. Description of the Related Art
When a processor or the like performs a normal operation, the operation can be switched to another operation by issuing an interrupt for interrupting the normal operation. In a computer system including a PCI (Peripheral Component Interconnect) bus, as a method for transmitting a notification representing an interrupt from a PCI device to a host processor, an MSI (Message Signaled Interrupt) method has been employed. The MSI method is used for an interrupt in a message format in a transaction layer of a packet base and is realized as a writing transaction using a double word. The PCI device capable of issuing the MSI includes an MSI address register and an MSI data register which accept data written by the host processor. Before receiving an interrupt from a certain PCI device as an MSI, the host processor sets an address to which the MSI is to be transmitted and data in the MSI address register and the MSI data register, respectively, included in the PCI device. When issuing the MSI, the PCI device transmits an interrupt notification to the address set in the MSI address register by issuing a PCI write transaction used to write a value set in the MSI data register. The host processor detects information representing that the data has been written to the specified address using an interrupt controller, for example, and recognizes the interrupt notification transmitted from the PCI device. Then, the host processor executes interrupt handler processing in accordance with the received MSI.
In a system in the related art, interrupt processing using an MSI is performed by setting an MSI address as an interrupt detection region and converting an MSI corresponding to the region into an interrupt signal to be transmitted to a processor (refer to Japanese Unexamined Patent Application Publication No. 2008-90375 (FIG. 5), for example).